With the continuous improvement of miniaturization, components and wiring technology have also made tremendous progress, such as high integration micro ICs packaged in BGA shells, and insulation spacing between conductors reduced to 0.5mm, these are just two examples. The wiring design of electronic components has an increasing impact on whether testing can be carried out well in the future production process. Below are several important rules and practical tips.

By adhering to certain regulations (DFT Design for Testability), the preparation and implementation costs of production testing can be greatly reduced. These regulations have been developed for many years, and of course, if new production and component technologies are adopted, they also need to be expanded and adapted accordingly. As the structural dimensions of electronic products become smaller and smaller, two particularly noteworthy issues have emerged: firstly, there are fewer and fewer accessible circuit nodes; Secondly, the application of methods such as In Circuit Test is limited. To address these issues, corresponding measures can be taken in the circuit layout, using new testing methods and innovative adapter solutions. The solution to the second problem also involves assigning additional tasks to the testing system that was originally used as an independent process. These tasks include programming memory components through testing systems or implementing integrated component self testing (Build in Self Test), BIST， Built in self testing. Transferring these steps to the testing system, overall, has created more added value. In order to smoothly implement these measures, corresponding considerations must be taken during the product research and development stage.

1. What is testability

The meaning of testability can be understood as: testing engineers can use the simplest possible methods to detect the characteristics of a certain component and see if it can meet the expected functions. Simply put, it means:

l          To what extent has the method of testing whether a product meets technical specifications been simplified?

l          How fast can testing programs be developed?

l          To what extent have product malfunctions been comprehensively identified?

l          To what extent is the method of accessing test points simplified?

In order to achieve good testability, design regulations for both mechanical and electrical aspects must be considered. Of course, achieving optimal testability requires a certain cost, but for the entire process flow, it has a series of benefits and is therefore an important prerequisite for the successful production of the product.

2. Why Develop Test Friendly Technologies

In the past, if a product could not be tested at the previous test point, the problem was simply pushed to the next test point. If a product defect cannot be detected during production testing, the identification and diagnosis of this defect will also be simply pushed into functional and system testing.

On the contrary, today people try to detect defects as early as possible, and its benefits are not only low cost, but more importantly, today's products are very complex, and some manufacturing defects may not be detected at all in functional testing. For example, certain components that require pre installation of software or programming may have such issues. (such as flash memory or ISPs: In System Programmable Devices). The programming of these components must be planned during the development phase, and the testing system must also master this programming.

Testing friendly circuit designs costs some money, however, designing circuits that are difficult to test will cost even more. Testing itself comes with costs, which increase with the number of test stages; The cost of testing is increasing from online testing to functional testing and system testing. If one of the tests is skipped, the cost may even be higher. The general rule is that the coefficient of increase for each additional level of testing cost is 10 times. By testing friendly circuit designs, faults can be detected early and the cost of testing friendly circuit designs can be quickly compensated.

3. How does file information affect testability

Only by fully utilizing the complete data and information in component development can it be possible to develop a testing program that can comprehensively detect faults. In many cases, close collaboration between the development and testing departments is necessary. The document information has an indisputable impact on testing engineers to understand component functions and develop testing strategies.

In order to avoid the problems caused by a lack of files and a lack of understanding of component functions, testing system manufacturers can rely on software tools that automatically generate test patterns based on random principles, or rely on non vector methods, which can only be considered as a temporary solution.

The complete documentation before testing includes parts lists, circuit design drawing data (mainly CAD data), and detailed information on the functions of relevant components (such as data sheets). Only by mastering all the information can it be possible to develop test vectors, define component failure styles, or make certain pre adjustments.

Some mechanical data is also important, such as those required to check the welding and positioning of components. Finally, for programmable components such as flash memory, PLD, FPGA, etc., if programming is not done during final installation and should be done on the testing system, it is also necessary to know their respective programming data. The programming data of the flash component should be complete and complete. If the flash chip contains 16Mbit of data, it should be possible to use 16Mbit, which can prevent misunderstandings and avoid address conflicts. For example, if a 4Mbit memory is used to provide only 300Kbit of data to a component, this situation may occur. Of course, data should be prepared in popular standard formats, such as Intel's Hex or Motorola's S record structure. Most testing systems, as long as they can program flash or ISP components, can interpret these formats. Many of the information mentioned earlier is also necessary for component manufacturing. Of course, there should be a clear distinction between manufacturability and testability, as these are completely different concepts that constitute different premises.

4. Mechanical contact conditions with good testability

Without considering the basic rules of mechanics, even circuits with very good testability in electrical aspects may be difficult to test. Many factors can limit the testability of electrical systems. If the test points are insufficient or too small, the probe bed adapter will have difficulty reaching every node of the circuit. If the position and size errors of the test points are too large, it will lead to poor testing repeatability. When using a probe bed adapter, attention should be paid to a series of suggestions regarding the size and positioning of the clamping holes and test points.

5. Electrical prerequisites for optimal testability

Electrical prerequisites are equally important for good testability as mechanical contact conditions, and both are indispensable. A gate circuit cannot be tested because it may not be able to reach the starting input through the test point, or it may be because the starting input is inside the packaging and cannot be contacted externally. In principle, both of these situations are not good, making testing impossible. When designing circuits, it should be noted that any component that needs to be tested using online testing methods should have some mechanism to enable each component to be electrically insulated. This mechanism can be achieved by disabling the input end, which can control the output end of the component in a static high ohmic state.

Although almost all testing systems can backdrive a node's state to any state, it is best to have a prohibited input terminal for the involved nodes. First, bring the node to a high ohmic state, and then "smoothly" add the corresponding level.

Similarly, the beat generator is always disconnected directly from the back of the oscillator by starting the lead, gate circuit, or plug-in bridge. The starting input terminal should never be directly connected to the circuit, but should be connected to the circuit through a 100 ohm resistor. Each component should have its own starting, resetting, or control lead pins. It is necessary to avoid sharing a resistor with the starting input of many components to connect to the circuit. This rule also applies to ASIC components, which should have a lead that can bring the output terminal to a high ohm state. If the component can be reset when the working voltage is turned on, it is also very helpful for the tester to trigger a reset. In this case, the component can be simply placed in the specified state before testing.

Unused component leads should also be accessible, as undetected short circuits in these areas can also cause component failures. In addition, unused gate circuits are often utilized for design improvements in the future, and they may be incorporated into the circuit. So equally important is that they should be tested from the beginning to ensure the reliability of their workpieces.

6. Improve testability

Suggestions for improving testability when using probe bed adapters

Secure the hole

l          Diagonal configuration

l          The positioning accuracy is ± 0.05mm (± 2mil)

l          The diameter accuracy is ± 0.076/-0mm (+3/-0mil)

l          The positioning accuracy relative to the test point is ± 0.05mm (± 2mil)

l          At least 3mm away from the edge of the component

l          Non permeable contact

Test points

l          As square as possible

l          The diameter of the test point should be at least 0.88mm (35mil)

l          The accuracy of the test point size is ± 0.076mm (± 3mil)

l          The interval accuracy between test points is ± 0.076mm (± 3mil)

l          The interval between test points should be as much as 2.5mm

l          Tin plated, the end face can be directly soldered

l          At least 3mm away from the edge of the component

l          All test points should potentially be located on the back of the plugin board

l          The test points should be evenly distributed on the plug-in board

l          Each node has at least one test point (100% channel)

l          Both backup and unused gate circuits have test points

l          Multiple external test points of the power supply are distributed in different locations

Component identification

l          Sign text in the same direction

l          Clear identification of model, version, serial number, and barcode

l          The component name should be clear and visible, and should be directly labeled as close to the component as possible

7. About Flash Memory and Other Programmable Components

The programming time for flash memory can sometimes be very long (up to 1 minute for large memory or memory groups). Therefore, reverse driving of other components is not allowed at this time, otherwise the flash memory may be damaged. To avoid this situation, all components connected to the control lines of the address bus must be placed in a high ohm state. Similarly, the data bus must also be able to be placed in an isolated state to ensure that the flash memory is empty and can be programmed in the next step.

There are some requirements for programmable components (ISPs) within the system, such as Altera, Products from companies such as XilinX and Lattuce, as well as other special requirements. In addition to ensuring the mechanical and electrical prerequisites for testability, it is also necessary to ensure the possibility of programming and verifying data. For Altera and Xilinx components, the Serial Vector Format (SVF) has been used, which has recently developed into an industry standard. Many testing systems can program such components and use input data in Serial Vector Format (SVF) for testing signal generators. These components are programmed using Boundary Scan Kette JTAG, and serial data formats are also programmed. When collecting programming data, it is important to consider all component chains in the circuit and not only restore the data to the components to be programmed. When programming, the automatic test signal generator takes into account the entire component chain and connects other components to the bypass model. On the contrary, Lattice requires the use of JEDEC format data and parallel programming through the usual input and output ends. After programming, the data is also used to check the functionality of the components. The data provided by the development department should be as convenient as possible for direct application of the testing system, or can be applied through simple conversion.

8. What should be noted for boundary scanning (JTAG)

Components based on complex components forming a fine grid provide testing engineers with only a few touchable test points. At this point, it is still possible to improve testability. Boundary scanning and integrated self testing techniques can be used to shorten testing completion time and improve testing effectiveness.

For development and testing engineers, a testing strategy based on boundary scanning and integrated self testing technology will definitely increase costs. Development engineers must use boundary scan components (IEEE-1149.1 standard) in circuits and find ways to make the corresponding specific test lead pins accessible (such as test data input-TDI, test data output-TDO, test clock frequency TKK, test mode selection TMS, and ggf. test reset). The testing engineer develops a boundary scan model (BSDL Boundary Scan Description Language) for the components. At this point, he must know what boundary scanning functions and instructions the components support. Boundary scan testing can diagnose short circuits and open circuits up to the lead level. In addition, if the development engineer has specified, automatic testing of components can be triggered through the boundary scan command "RunBIST". Especially when there are many ASICs and other complex components in the circuit, there is no conventional testing model for these components. By using boundary scanning components, the cost of developing a testing model can be greatly reduced.

The degree of time and cost reduction varies for each component. For a circuit with an IC, if 100% detection is required, approximately 400000 test vectors are needed. By using boundary scanning, the number of test vectors can be reduced to hundreds at the same fault detection rate. Therefore, the boundary scan method has special advantages in the absence of a test model or when the nodes in contact with the circuit are restricted. Whether to use boundary scanning depends on the additional costs incurred during development, utilization, and manufacturing processes. Boundary scanning must balance the time required to detect faults, testing time, time to enter the market, and adapter costs, and strive to save as much as possible. In many cases, mixing traditional online testing methods with boundary scan methods is the best solution for the salt industry.